MODELING OF CONCURRENT EXECUTION

Abstract

A parallel-execution model (PEM) new approach that simulates concurrent parallelism in parallel programs is presented. The approach uses VHDL (VHSIC Hardware Description Language) as the modeling tool. The PEM approach consists of two components: The first component is an IF1 parser. The parser takes a dataflow graph represented by the IF1 (Intermediate Form 1) dataflow language as an input and produces Java objects as an output. The second component is an IF1-to-VHDL compiler. This compiler takes the Java objects produced by the IF1 parser as an input and produces the corresponing VHDL code that reprersents the graph as an output. To validate our approach we apply the VHDL simulator to simulate the resultant code and get the PEM performance metrics. Simulation results show that our model is accurate and powerful and the results coinside with the expectations.